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cstart description:

Cstart.asm sets up the rabbit to run C code and jumps to main. It is written to be generic, but there are some customizations that may be needed.

Probably the most confusing part is the memory map. Cstart tries to set things up for optimum speed.

The rabbit has 4, 256k quadrants for memory. These are set up as follows:

Module Flash/RAM	0000-3FFFF	40000-7FFFF	80000-BFFFF	C0000-FFFF	Typical Module
256/128	Flash	repeat Flash	128k RAM	repeat RAM	RCM2200
512/256	Flash	Flash	RAM	Repeat RAM	RCM3720
512/512	Flash	Flash	RAM	RAM	RCM3700
512/512+256	Fast RAM	Fast RAM	Slow RAM	Top 256k Flash	RCM3200
512/512+512	Fast RAM	Fast RAM	Slow RAM	Slow RAM	RCM3300

Modules that are faster than 40mHz need wait-states for Flash. These modules have 0-ws Fast RAM to allow the CPU to run full speed. If cstart detects a module >40mHz, it copies the Flash to Fast RAM. Note, in the case of boards with Fast RAM, the debug memory map will be identical to a started from Flash.

Note, the Flash is not in the memory map for devices with lots of RAM. This is anot a problem, The ReadFlash() and WriteFlash() routines will map the RAM in as needed to do the read/write (1.68 and later.)

Normally you would not want to modify the memory map. For custom boards you may want to. There are several defines for this:

	.ifndef	MB0CRval
;
MB0CRval	.equ	WS0 | 8	; MB0CR: 0 ws, OE0, CS0 active, WP enabled
MB1CRval	.equ	WS0 | 8	; MB1CR: 0 ws, OE0, CS0 active, WP enabled
MB1CRXval	.equ	WS0 | 10; MB1CR: 0 ws, OE0, CS2 active, WP enabled
;
MB2CRval	.equ	WS0 | 5	; MB2CR: 1 ws, OE1, WE1, CS1 active
MB3CRval	.equ	WS0 | 5	; MB3CR: 1 ws, OE1, WE1, CS1 active
;
	.endif

Notice the .ifndef MB0CRval. These can be defined in the project to override the settings without the need to modify the cstart.asm file. Also notice that all the chip selects have 0 wait states. The MB0CRval must be 0 wait states for the speed calculation to work.

The MB0CRval is for the first 256k. MB1CRval for second and so on up to MB3CRval.

The MB1CRval is assigned to the second 256k on a 512k Flash chip by default. If it detects a 256k Flash in the first 256k, it will assign MB1CRXval to the second 256k.

Note, some versions of cstart.asm will set Fast RAM to 1ws whan it should be 0. The following code at the start of main() can set 0ws:

#asm
    ; set 0ws since we are in fast RAM
    ld  e,MB0CR
    ld  hl,_srMB0CR##
    set 6,(hl)          ; 0ws 512k ram
    ioi ldi
    nop
    set 6,(hl)          ; 0ws 512k ram
    ioi ldi
#endasm

The function enableClockDoubler() will set the number of wait states as needed. There is no need to set the number of wait states manually. If you need to change the default settings, it is best to modify setwaitstates.asm and include it with your project.

CSTART Defines

The wizard will set some defines in the project for cstart.asm. These can be overriden if needed. These are as follows:

STACK_SIZE - size of stack, the default of 512 may be too small for TCP/IP.

INC_DEBUG - set to 0 to not include the support for the debugger. The .bin file will be almost 2k smaller, but i can not be debugged. Normally this is set to 1 unless Flash space is real tight.

GEN_CRC - Set to 1 to enable CRC checks of Flash segments.

STARTUP_SEG - Uses a sec called STARTUP that contains a list of functions to call before main(). This was a hack to implement some of DC GLOBAL_INIT{} functionality. It shouldlbe avoided as it make debugging difficult and is complicated to configure.

DISABLE_CLOCK_DOUBLER - Normally undefined. Almost all boards use the clock doubler for normal operation.

The above defines should be made in the options for cstart.asm or for the model options.

..iTbl:

..iTbl: is a list of initializations that are done early in cstart. These are formatted as IO Address, Value pairs. If you have a board that needs rabbit I/O pins set to a specific value early on boot, add them to this table. Note: any Rabbit registers that are added to this table need to be removed from ..zTbl: or it will be zeroed after the ..iTbl is called.

Also none of these set up the shadow regs that are normally are initilaized as 0. They may need to be initilaised to match your changes to cstart.

Custom boards >=44mHz that run from Flash

Look for the following code at about line 516:

	cp	a,36			; > 44MHz?
	jr	c,..noCpy		; Skip if not
	ex	af,af'

Change the jr c,..noCpy to jr ..noCpy . This will prevent the copy to RAM and the MBxCRval settings will be used..